AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 897

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.4.3.1
Figure 32-1. Manual and Automatic Modes when MR.LOD is zero
Figure 32-2. Manual and Automatic Modes when MR.LOD is one
32.4.3.2
32072C–AVR32–2010/03
Manual and automatic modes
DMA mode
The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read.
If the user does not want to read the output data registers between each encryption/decryption,
the ISR.DATRDY bit will not be cleared. If the ISR.DATRDY bit is not cleared, the user cannot
know the end of the following encryptions/decryptions.
The ISR.DATRDY bit is cleared when at least one IDATAnR register is written, so before the
start of a new transfer. No more ODATAnR register reads are necessary between consecutive
encryptions/decryptions.
The end of the encryption/decryption should be monitored with the DMA Controller.
ISR.DATRDY
ISR.DATRDY
• When MR.LOD is zero
• When MR.LOD is one
• when MR.LOD is zero
Write IDATAnR register(s) (Auto mode)
Write IDATAnR register(s) (Auto mode)
Write CR.START(Manual mode)
Write CR.START (Manual mode)
or
Or
Encryption or Decryption Process
Encryption or Decryption Process
Read ODATAnR register(s)
Write IDATAnR register(s)
AT32UC3A3/A4
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