AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 862

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• DTIP: Data Transfer in Progress
• BLKE: Data Block Ended
• TXRDY: Transmit Ready
• RXRDY: Receiver Ready
• CMDRDY: Command Ready
32072C–AVR32–2010/03
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data
transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line
(DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer
block length becomes free.
The NOTBUSY bit allows to deal with these different states.
1: MCI is ready for new data transfer.
0: MCI is not ready for new data transfer.
This bit is cleared at the end of the card response.
This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
This bit is set when the current data transfer is in progress.
This bit is cleared at the end of the CRC16 calculation
1: The current data transfer is still in progress.
0: No data transfer in progress.
This bit must be used only for Write Operations.
This bit is set when a data block transfer has ended.
This bit is cleared when reading SR.
1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status.
0: A data block transfer is not yet finished.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
This bit is set when the last data written in the TDR register has been transferred.
This bit is cleared the last data written in the TDR register has not yet been transferred.
This bit is set when the data has been received since the last read of the RDR register.
This bit is cleared when the data has not yet been received since the last read of the RDR register.
This bit is set when the last command has been sent.
This bit is cleared when writing the CMDR register
AT32UC3A3/A4
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