AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 333

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32072C–AVR32–2010/03
Figure 19-11. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS
registers. This put the DMACA into Row 1 as shown in
the next block is not the last block in the DMA transfer, then the reload bits should
remain enabled to keep the DMACA in Row 4.
masked (MaskBlock[x] = 1’b0, where x is the channel number), then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the
DMACA into ROW 1 of
transfer has completed. The transfer is similar to that shown in
page
Source Layer
Address of
333. The DMA transfer flow is shown in
SAR
Source Blocks
Table 19-1 on page 324
Block2
Block0
Block1
BlockN
Destination Blocks
Figure 19-12 on page
before the last block of the DMA
Table 19-1 on page
AT32UC3A3/A4
Destination Layer
DAR
Address of
Figure 19-11 on
334.
324. If
333