AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 738

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.8.3.13
Register Name:
Access Type:
Offset:
Reset Value:
• PBYCT: Pipe Byte Count
• CFGOK: Configuration OK Status
• RWALL: Read/Write Allowed
• CURRBK: Current Bank
32072C–AVR32–2010/03
PACKETI
SHORT
31
23
15
7
-
This field contains the byte count of the FIFO.
For OUT pipe, incremented after each byte written by the user into the pipe and decremented after each byte sent to the
peripheral.
For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user from
the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
This bit is set/cleared when the UPCFGn.ALLOC bit is set.
This bit is set if the pipe n number of banks (UPCFGn.PBK) and size (UPCFGn.PSIZE) are correct compared to the maximal
allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values ot the PBK and PSIZE field in the UPCFGn register.
For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALL or the PERR bit is one.
For non-control pipe, this field indicates the number of the current bank.
0
CURRBK
Pipe n Status Register
CURRBK
RXSTALLDI/
CRCERRI
30
22
14
6
UPSTAn, n in [0..7]
Read-Only
0x0530 + (n * 0x04)
0x00000000
PBYCT[3:0]
0
OVERFI
29
21
13
5
Current Bank
Bank0
NBUSYBK
NAKEDI
28
20
12
4
PBYCT[10:4]
PERRI
27
19
11
3
-
-
UNDERFI
TXSTPI/
CFGOK
26
18
10
2
-
AT32UC3A3/A4
TXOUTI
25
17
9
1
-
DTSEQ
RWALL
RXINI
24
16
8
0
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