AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 898

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 32-3. DMA Mode when MR.LOD is zero
Figure 32-4. DMA Mode when MR.LOD is one
Table 32-3.
Note:
Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results.
32072C–AVR32–2010/03
ISR.DATRDY bit Clearing
Encryption/Decryption
Encrypted/Decrypted
Data Result Location
Condition
1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR)
End of
definition.
Last Output Mode Behavior versus Start Modes
(1)
The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that
the encryption/decryption is completed.
In this case, no receive buffers are required.
The output data is only available in ODATAnR registers.
Following table summarizes the different cases.
D M A C o n tro lle r In te rru p t
DMA Controller Interrupt
At least one ODATAnR
In ODATAnR registers
register must be read
• when MR.LOD is one
ISR.DATRDY
MR.LOD = 0
ISR.DATRDY
Manual and Automatic Modes
E n a b le D M A C o n tro lle r C h a n n e ls (R e ce ive a n d T ra n sm it C h a n n e ls )
Enable DMA Controller Channels (only Transmit Channel)
register must be written
In ODATAnR registers
At least one IDATAnR
Multiple Encryption or Decryption Processes
M u ltip le e n cryp tio n o r d e c ryp tio n p ro ce ss e s
ISR.DATRDY
MR.LOD = 1
DMA Controller
configuration of
DMA Controller
specified in the
At the address
MR.LOD = 0
Not used
Interrupt
AT32UC3A3/A4
DMA Mode
Managed by the
In ODATAnR registers
DMA Controller
Interrupt then
MR.LOD = 1
DATRDY.ISR
Controller
DMA
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