AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 514

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.7.6
24.7.6.1
24.7.7
32072C–AVR32–2010/03
Receive Compare Modes
Data Framing Format
Compare functions
and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge
detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).
Figure 24-12. Receive Compare Modes
Compare 0 can be one start event of the receiver. In this case, the receiver compares at each
new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI,
RFMR.FSLEN} lower bits of the data contained in the Receive Compare 0 Register (RC0R).
When this start event is selected, the user can program the receiver to start a new data transfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP).
The data framing format of both the transmitter and the receiver are programmable through the
TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select:
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to
the Frame Sync Data Enable and the Data Default Value bits in the TFMR register
(TFMR.FSDEN and TFMR.DATDEF).
Table 24-3.
• the event that starts the data transfer (RCMR.START and TCMR.START)
• the delay in number of bit periods between the start event and the first data bit
• the length of the data (RFMR.DATLEN and TFMR.DATLEN)
• the number of data to be transferred for each start event (RFMR.DATNB and TFMR.DATLEN)
• the length of synchronization transferred for each start event (RFMR.FSLENHI,
• the bit sense: most or lowest significant bit first (RFMR.MSBF and TFMR.MSBF)
Transmitter
(RCMR.STTDLY and TCMR.STTDLY)
RFMR.FSLEN, TFMR.FSLENHI, and TFMR.FSLEN)
TCMR
TCMR
TCMR
RX_CLOCK
RX_DATA
Data Framing Format Registers
(Input)
Receiver
RCMR
RCMR
RCMR
CMP0
(4 in This Example)
{FSLENHI,FSLEN}
CMP1
Up to 256 Bits
Bit/Field
PERIOD
STTDLY
START
CMP2
CMP3
Start
Up to 512
Up to 255
Length
STTDLY
Ignored
Frame size
Start selection
Size of transmit start delay
AT32UC3A3/A4
B0
Comment
DATLEN
B1
B2
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