AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 316

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32072C–AVR32–2010/03
Transfer hierarchy:
fers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for
non-memory peripherals.
Figure 19-2. DMACA Transfer Hierarchy for Non-Memory Peripheral
Figure 19-3. DMACA Transfer Hierarchy for Memory
Block: A block of DMACA data. The amount of data (block length) is determined by the flow
controller. For transfers between the DMACA and memory, a block is broken directly into a
sequence of System Bus bursts and single transfers. For transfers between the DMACA and a
non-memory peripheral, a block is broken into a sequence of DMACA transactions (single and
bursts). These are in turn broken into a sequence of System Bus transfers.
Transaction: A basic unit of a DMACA transfer as determined by either the hardware or soft-
ware handshaking interface. A transaction is only relevant for transfers between the DMACA
and a source or destination peripheral if the source or destination peripheral is a non-memory
device. There are two types of transactions: single and burst.
System Bus
Transaction
Transfer
Burst
Block
Burst
System Bus
Transfer
Burst
Block
System Bus
Transaction
Transfer
Burst
Figure 19-2 on page 316
Burst
Block
System Bus
DMAC Transfer
Figure 19-3 on page 316
Transfer
Burst
Block
DMAC Transfer
System Bus
Transfer
Transaction
Burst
Burst
System Bus
Transfer
Block
Burst
System Bus
illustrates the hierarchy between DMACA trans-
Transfer
Single
Block
shows the transfer hierarchy for memory.
System Bus
Transfer
Single
System Bus
Transaction
Transfer
Single
Single
AT32UC3A3/A4
Block Transfer
Level
System Bus
Transfer Level
DMA Transfer
Level
Block Transfer
Level
DMA Transaction
Level
System Bus
Transfer Level
DMA Transfer
Level
316