AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 719

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.8.2.19
Register Name:
Access Type:
Offset:
Reset Value:
• CHBYTELENGTH: Channel Byte Length
• BURSTLOCKEN: Burst Lock Enable
• DESCLDIRQEN: Descriptor Loaded Interrupt Enable
• EOBUFFIRQEN: End of Buffer Interrupt Enable
• EOTIRQEN: End of USB Transfer Interrupt Enable
• DMAENDEN: End of DMA Buffer Output Enable
32072C–AVR32–2010/03
BURSTLOCKEN
31
23
15
7
-
This field determines the total number of bytes to be transferred for this buffer.
The maximum channel transfer size 64kB is reached when this field is zero (default value).
If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.
This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is
ignored.
1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration.
0: The DMA never locks the HSB access.
1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system
bus.
0: The Descriptor Loaded interrupt is disabled.
1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.
0: The end of buffer interrupt is disabled.
1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.
0: The end of usb OUT data transfer interrupt is disabled.
Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (or a Zero Length Packet) will be sent to the USB line to properly closed the usb
transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
Device DMA Channel n Control Register
DESCLDIRQEN
30
22
14
6
-
UDDMAnCONTROL, n in [1..7]
Read/Write
0x0318 + (n - 1) * 0x10
0x00000000
EOBUFFIRQEN
29
21
13
5
-
EOTIRQEN
CHBYTELENGTH[15:8]
CHBYTELENGTH[7:0]
28
20
12
4
-
DMAENDEN
27
19
11
3
-
BUFFCLOSE
INEN
26
18
10
2
-
LDNXTCH
AT32UC3A3/A4
DESCEN
25
17
9
1
-
CHEN
24
16
8
0
-
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