AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 878

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 31-6. Interface mode switching sequence
31.6.4
31.6.5
32072C–AVR32–2010/03
Data transfer requests
Interrupts
After the communication protocol with the Memory Stick starts, a data transfer request is
asserted to the CPU (DRQ bit in ISR) and to DMACA (internal signals), until data transfer of the
amount indicated by DSZ (CMD) is finished. However, the data transfer request stops when the
internal FIFO becomes either empty or full.
Like CPU, DMACA uses Peripheral Bus to access FIFO so it is not recommended to access MSI
registers during transfer. It is also not recommended to enable DRQ interrupt because ISR.DRQ
bit is automatically cleared when FIFO is accessed.
DMACA channel should be configured first and the data size should be a multiple of 64 bits
(FIFO size is 4 * 64bits).
The interrupt sources of MSI are :
•
•
•
•
•
•
Each interrupt source can be enabled in Interrupt Enable register (IER) and disabled in Interrupt
Disable register (IDR). The enable status is read in Interrupt Mask register (IMR). The status of
the interrupt source, even if the interrupt is masked, can be read in ISR.
PEND : protocol command ended without error.
DRQ : data request, FIFO is full or empty.
MSINT : interrupt received from Memory Stick.
CRC : protocol ended with CRC error.
TOE : protocol ended with time out error.
CD : card detected (inserted or removed).
SET_R/W_REG_ADRS TPC
(
(
Set Parallel Interface Mode
MSSYS.SRAC=1, MSSYS.REI=1)
MSSYS.SRAC=0, MSSYS.REI=0)
Serial Interface Mode
(
WRITE_REG TPC
MSSYS.CLKDIV[7:0]=X)
system parameter
Change SCLK
(PAM bit)
OK
Error
AT32UC3A3/A4
878