AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 640

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.7.1.5
26.7.1.6
32072C–AVR32–2010/03
Speed control
DPRAM management
•USB Suspend mode
•Device mode
•Host mode
In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register
(UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the transceiver
is automatically set in suspend mode to reduce the consumption.The 480MHz internal PLL is
stopped. The USBSTA.CLKUSABLE bit is cleared.
When the USB interface is in device mode, the speed selection (full-speed or high-speed) is per-
formed automatically by the USBB during the USB reset according to the host speed capability.
At the end of the USB reset, the USBB enables or disables high-speed terminations and pull-up.
It is possible to restraint the USBB to full-speed or low-speed mode by handling the LS and the
Speed Configuration (SPDCONF) bits in UDCON.
When the USB interface is in host mode, internal pull-down resistors are connected on both D+
and D- and the interface detects the speed of the connected device, which is reflected by the
Speed Status (SPEED) field in USBSTA.
Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the
last pipe/endpoint to be allocated). The user shall therefore configure them in the same order.
The allocation of a pipe/endpoint n starts when the Endpoint Memory Allocate bit in the Endpoint
n Configuration register (UECFGn.ALLOC) is written to one. Then, the hardware allocates a
memory area in the DPRAM and inserts it between the n-1 and n+1 pipes/endpoints. The n+1
pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/end-
point memory windows (from n+2) do not slide.
Disabling a pipe, by writing a zero to the Pipe n Enable bit in the Pipe Enable/Reset register
(UPRST.PENn), or disabling an endpoint, by writing a zero to the Endpoint n Enable bit in the
Endpoint Enable/Reset register (UERST.EPENn), resets neither the UECFGn.ALLOC bit nor its
configuration (the Pipe Banks (PBK) field, the Pipe Size (PSIZE) field, the Pipe Token (PTO-
KEN) field, the Pipe Type (PTYPE) field, the Pipe Endpoint Number (PEPNUM) field, and the
Pipe Interrupt Request Frequency (INTFRQ) field in the Pipe n Configuration (UPCFGn) regis-
ter/the Endpoint Banks (EPBK) field, the Endpoint Size (EPSIZE) field, the Endpoint Direction
(EPDIR) field, and the Endpoint Type (EPTYPE) field in UECFGn).
To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/end-
point memory window then slides down and its data is lost. Note that the following pipe/endpoint
memory windows (from n+2) does not slide.
• The ID Transition Interrupt (IDTI)
• The VBus Transition Interrupt (VBUSTI)
• The Wake-up Interrupt (WAKEUP)
• The Host Wake-up Interrupt (HWUPI)
AT32UC3A3/A4
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