AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 57

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.6.3
Name:
Access Type:
Offset:
Reset Value:
• MASK: Clock Mask
Table 7-7.
32072C–AVR32–2010/03
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
23
15
7
CPUMASK
-
OCD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current
power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is
shown in
Clock Mask Registers
(1)
Maskable module clocks in AT32UC3A3.
Table 7-7 on page
30
22
14
CPU/HSB/PBA/PBBMASK
Read/Write
0x08-0x14
0x00000003/0x00000FFF/0x001FFFFF/0x000003FF
6
HSBMASK
FLASHC
PBA Bridge
PBB Bridge
USBB
PDCA
EBI
PBC Bridge
DMACA
BUSMON
HRAMC0
HRAMC1
(2)
-
-
-
-
57.
29
21
13
5
28
20
12
4
MASK[31:24]
MASK[23:16]
PBAMASK
INTC
I/O
PDCA
PM/RTC/EIC
ADC
SPI0
SPI1
TWIM0
TWIM1
TWIS0
TWIS1
USART0
USART1
USART2
USART3
SSC
MASK[15:8]
MASK[7:0]
27
19
11
3
PBBMASK
HMATRIX
USBB
FLASHC
SMC
SDRAMC
ECCHRS
MCI
BUSMON
MSI
AES
-
-
-
-
-
-
26
18
10
2
AT32UC3A3/A4
25
17
9
1
24
16
8
0
57