AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 847

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30.7.2
Name:
Access Type:
Offset:
Reset Value:
• BLKLEN[15:0]: Data Block Length
• PADV: Padding Value
• FBYTE: Force Byte Transfer
• WRPROOF Write Proof Enable
• RDPROOF Read Proof Enable
32072C–AVR32–2010/03
31
23
15
7
-
This field determines the size of the data block.
This field is also accessible in the BLKR register.
If FBYTE bit is zero, the BLKEN[1:0] field must be written to 0b00
0: 0x00 value is used when padding data in write transfer.
1: 0xFF value is used when padding data in write transfer.
PADV is used only in manual transfer.
Enabling Force Byte Transfer allows byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
Writing a one to this bit will enable the Force Byte Transfer.
Writing a zero to this bit will disable the Force Byte Transfer.
Enabling Write Proof allows to stop the MCI Clock (CLK) during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Write Proof mode.
Writing a zero to this bit will disable the Write Proof mode.
Enabling Read Proof allows to stop the MCI Clock (CLK) during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Read Proof mode.
Writing a zero to this bit will disable the Read Proof mode.
Mode Register
PADV
30
22
14
6
MR
Read-write
0x004
0x00000000
Notes:
FBYTE
1. In SDIO Byte mode, BLKLEN field is not used.
2. BLKLEN should be written to one before sending the data transfer command. Otherwise,
29
21
13
5
Overrun may occur even if RDPROOF bit is one.
WRPROOF
28
20
12
4
BLKLEN[15:8]
BLKLEN[7:0]
CLKDIV
RDPROOF
27
19
11
3
26
18
10
2
AT32UC3A3/A4
PWSDIV
25
17
9
1
24
16
8
0
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