AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 652

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.7.2.13
32072C–AVR32–2010/03
Management of OUT endpoints
•Detailed description
•Overview
The data is written, following the next flow:
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following bank may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on
Figure 26-18. Abort Algorithm
OUT packets are sent by the host. All the data can be read which acknowledges or not the bank
when it is empty.
The endpoint must be configured first.
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
• The user acknowledges the interrupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
• The user allows the controller to send the bank and switches to the next bank (if any) by
TXINE is one.
(USBFIFOnDATA) register, until all the data frame is written or the bank is full (in which case
RWALL is cleared and the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
clearing FIFOCON.
Figure 26-18 on page
TXINEC = 1
EPRSTn = 1
Abort Done
NBUSYBK
Endpoint
Abort
== 0?
Yes
No
Yes
652.
KILLBKS = 1
KILLBK
No
== 1?
Disable the TXINI interrupt.
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Wait for the end of the
procedure
Kill the last written bank.
AT32UC3A3/A4
652