AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 852

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30.7.6
Name:
Access Type:
Offset:
Reset Value:
• BOOT_ACK: Boot Operation Acknowledge
• ATACS: ATA with Command Completion Signal
• IOSPCMD: SDIO Special Command
32072C–AVR32–2010/03
IOSPCMD
31
23
15
7
-
-
-
This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an
interrupt response (SPCMD field). This means that the current command execution cannot be interrupted or modified.
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is isssued.
Writing a one to this bit indicates that a Boot acknolwedge is expected within a programmable amount of time defined with
DTOMUL and DTOCYC fields located in the DTOR register. If the acknowledge pattern is not received then an acknowledge
timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.
Writing a one to this bit will configure ATA completion signal within a programmed amount of time in Completion Signal Time-out
Register (CSTOR).
Writing a zero to this bit will configure no ATA completion signal.
0
1
2
3
Command Register
RSPTYP
SDIO Special Command Type
Not a SDIO Special Command
SDIO Suspend Command
SDIO Resume Command
Reserved
30
22
14
6
-
-
-
CMDR
Write-only
0x014
0x00000000
29
21
13
5
-
-
MAXLAT
TRTYP
28
20
12
4
-
BOOTACK
OPDCMD
27
19
11
3
CMDNB
ATACS
TRDIR
26
18
10
2
AT32UC3A3/A4
SPCMD
25
17
9
1
IOSPCMD
TRCMD
24
16
8
0
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