AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 641

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32072C–AVR32–2010/03
U(P/E)RST.(E)PENn = 1
U(P/E)CFGn.ALLOC = 1
Pipes/Endpoints 0..5
Free Memory
Activated
Figure 26-7 on page 641
example.
Figure 26-7. Allocation and Reorganization of the DPRAM
Note that:
PEP5
PEP4
PEP3
PEP2
PEP1
PEP0
1. The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order.
2. The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller.
3. In order to free its memory, its ALLOC bit is written to zero. The pipe/endpoint 4 mem-
4. If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller
• There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as
• Deactivating then reactivating a same pipe/endpoint with the same configuration only
• When the user write a one to the ALLOC bit, the Configuration OK Status bit in the Endpoint
memory allocation and de-allocation may affect only higher pipes/endpoints.
modifies temporarily the controller DPRAM pointer and size for this pipe/endpoint, but
nothing changes in the DPRAM, so higher endpoints seem to not have been moved and their
data is preserved as far as nothing has been written or received into them while changing the
allocation state of the first pipe/endpoint.
n Status register (UESTAn.CFGOK) is set only if the configured size and number of banks
are correct compared to their maximal allowed values for the endpoint and to the maximal
FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory
allocation conflicts.
Each pipe/endpoint then owns a memory area in the DPRAM.
ory window slides down, but the pipe/endpoint 5 does not move.
allocates a memory area after the pipe/endpoint 2 memory area and automatically
slides up the pipe/endpoint 4 memory window. The pipe/endpoint 5 does not move and
a memory conflict appears as the memory windows of the pipes/endpoints 4 and 5
overlap. The data of these pipes/endpoints is potentially lost.
U(P/E)RST.(E)PEN3 = 0
Pipe/Endpoint 3
(ALLOC stays at 1)
Free Memory
Disabled
PEP5
PEP4
PEP3
PEP2
PEP1
PEP0
illustrates the allocation and reorganization of the DPRAM in a typical
U(P/E)CFG3.ALLOC = 0
Pipe/Endpoint 3
PEP4 Lost Memory
Memory Freed
Free Memory
PEP5
PEP4
PEP2
PEP1
PEP0
U(P/E)RST.(E)PEN3 = 1
U(P/E)CFG3.ALLOC = 1
AT32UC3A3/A4
Pipe/Endpoint 3
PEP3 (larger size)
Free Memory
Activated
PEP4
PEP2
PEP1
PEP0
PEP5
Conflict
641