AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 659

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.7.3.6
26.7.3.7
32072C–AVR32–2010/03
Pipe activation
Address setup
The pipe is maintained inactive and reset (see
disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset.
The algorithm represented on
pipe.
Figure 26-23. Pipe Activation Algorithm
As long as the pipe is not correctly configured (UPSTAn.CFGOK is zero), the controller can not
send packets to the device through this pipe.
The UPSTAn.CFGOK bit is set only if the configured size and number of banks are correct com-
pared to their maximal allowed values for the pipe (see
maximal FIFO size (i.e. the DPRAM size).
See
Once the pipe is correctly configured (UPSTAn.CFGOK is zero), only the PTOKEN and INTFRQ
fields can be written by software. INTFRQ is meaningless for non-interrupt pipes.
When starting an enumeration, the user gets the device descriptor by sending a
GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the
device default control endpoint (bMaxPacketSize0) and the user re-configures the size of the
default control pipe with this size parameter.
Once the device has answered the first host requests with the default device address 0, the host
assigns a new address to the device. The host controller has to send an USB reset to the device
and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the
device. Once this SETUP transaction is over, the user writes the new address into the USB Host
Address for Pipe n field in the USB Host Device Address register (UHADDR.UHADDRPn). All
following requests, on all pipes, will be performed using this new address.
Section 26.7.1.6
Pipe Activated
Yes
CFGOK ==
Activation
PENn = 1
UPCFGn
PEPNUM
PTOKEN
INTFRQ
PTYPE
ALLOC
PSIZE
Pipe
for more details about DPRAM management.
PBK
1?
Figure 26-23 on page 659
No
ERROR
Section 26.7.3.5
Configure the pipe:
Allocate the configured DPRAM banks.
Test if the pipe configuration is
correct.
Enable the pipe.
- interrupt request frequency
- endpoint number
- type
- size
- number of banks
must be followed in order to activate a
Table 26-1 on page
for more details) as long as it is
AT32UC3A3/A4
630) and to the
659