AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 636

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.7
26.7.1
26.7.1.1
26.7.1.2
32072C–AVR32–2010/03
Functional Description
USB General Operation
Introduction
Power-On and reset
After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device
mode or in host mode according to the ID detection.
If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status
register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by
the I/O Controller) and device mode is engaged.
The USBSTA.ID bit is cleared when a low level has been detected on the USB_ID pin. Host
mode is then engaged.
Figure 26-5 on page 636
Figure 26-5. General States
After a hardware reset, the USBB is in the Reset state. In this state:
• The macro is disabled. The USBB Enable bit in the General Control register
• The macro clock is stopped in order to minimize power consumption. The Freeze USB Clock
• The UTMI is in suspend mode.
• The internal states and registers of the device and host modes are reset.
• The DPRAM is not cleared and is accessible.
• The USBSTA.ID bit and the VBus Level bit in the UBSTA (UBSTA.VBUS) reflect the states of
• The OTG Pad Enable (OTGPADE) bit, the VBus Polarity (VBUSPO) bit, the FRZCLK bit, the
(USBCON.USBE) is zero.
bit in USBCON (USBON.FRZCLK) is set.
the USB_ID and USB_VBUS input pins.
USBE bit, the USB_ID Pin Enable (UIDE) bit, the USBB Mode (UIMOD) bit in USBCON, and
the Low-Speed Mode Force bit in the Device General Control (UDCON.LS) register can be
written by software, so that the user can program pads and speed before enabling the macro,
but their value is only taken into account once the macro is enabled and unfrozen.
describes the USBB main states.
Clock stopped:
FRZCLK = 1
Device
Macro off:
USBE = 0
USBE = 1
ID = 1
USBE = 0
Reset
USBE = 1
ID = 0
USBE = 0
USBE = 0
Host
RESET
HW
<any
other
state>
AT32UC3A3/A4
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