AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 328

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32072C–AVR32–2010/03
Note:
Note:
4. Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the
5. Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the
6. Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory
7. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI
8. Clear any pending interrupts on the channel from the previous DMA transfer by writing
9. Program the CTLx, CFGx registers according to Row 10 as shown in
10. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
11. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
12. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
13. Source and destination request single and burst DMA transactions to transfer the block
14. The DMACA does not wait for the block interrupt to be cleared, but continues fetching
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
last) are set as shown in Row 10 of
the last Linked List Item must be set as described in Row 1 or Row 5 of
page
last) are non-zero and point to the base address of the next Linked List Item.
point to the start source/destination block address preceding that LLI fetch.
entries in memory are cleared.
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
page
performed.
of data (assuming non-memory peripheral). The DMACA acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
the next LLI from the memory location pointed to by current LLPx register and automat-
ically reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA
transfer continues until the DMACA determines that the CTLx and LLPx registers at the
end of a block transfer match that described in Row 1 or Row 5 of
324. The DMACA then knows that the previous block transferred was the last block in
the DMA transfer. The DMA transfer might look like that shown in
329.
The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automati-
cally reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0).
Table 19-1 on page 324
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
peripheral, assign the handshaking interface to the source and destination periph-
eral. This requires programming the SRC_PER and DEST_PER bits, respectively.
324.
324.
Figure 19-9 on page 330
Table 19-1 on page
shows a Linked List example with two list items.
324. The LLI.CTLx register of
AT32UC3A3/A4
Figure 19-8 on page
Table 19-1 on page
Table 19-1 on
Table 19-1 on
328