AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 607

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

•
Table 25-20.
•
Table 25-21.
•
Table 25-22.
32072C–AVR32–2010/03
CHRL: Character Length.
USCLKS: Clock Selection
MODE
0
0
1
1
SYNC = 0: USART operates in Asynchronous Mode.
SYNC = 1: USART operates in Synchronous Mode.
If USART operates in SPI Mode (MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with
CPOL to produce the required clock/data relationship between master and slave devices.
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
USCLKS
CHRL
0
1
0
1
0
0
0
0
1
1
0
0
0
1
1
Note:
0
1
0
1
MODE
Others
1. The value of DIV is device dependent. Please refer to the Module Configuration section at the
Character Length
5 bits
6 bits
7 bits
8 bits
end of this chapter.
Selected Clock
CLK_USART
CLK_USART/DIV
Reserved
CLK
0
0
1
1
0
1
0
1
1
1
1
(1)
0
1
0
1
0
0
0
0
1
0
1
Mode of the USART
Normal
RS485
Hardware Handshaking
Modem
IS07816 Protocol: T = 0
IS07816 Protocol: T = 1
IrDA
LIN Master
LIN Slave
SPI Master
SPI Slave
Reserved
AT32UC3A3/A4
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