AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 630

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26. Hi-Speed USB On-The-Go Interface (USBB)
26.1
26.2
Table 26-1.
32072C–AVR32–2010/03
Pipe/Endpoint
Features
Overview
0
1
2
3
4
5
6
7
Description of USB Pipes/Endpoints
Mnemonic
Rev: 3.2.0.5
•
•
•
•
•
•
•
•
The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0
specification, in all speeds.
Each pipe/endpoint can be configured in one of several transfer types. It can be associated with
one or more banks of a dual-port RAM (DPRAM) used to store the current data payload. If sev-
eral banks are used (“ping-pong” mode), then one DPRAM bank is read or written by the CPU or
the DMA while the other is read or written by the USBB core. This feature is mandatory for iso-
chronous pipes/endpoints.
Table 26-1 on page 630
PEP0
PEP1
PEP2
PEP3
PEP4
PEP5
PEP6
PEP7
The theoretical maximal pipe/endpoint configuration (458752) exceeds the real DPRAM size
(2368). The user needs to be aware of this when configuring pipes/endpoints. To fully use the
Compatible with the USB 2.0 specification
Supports High (480Mbit/s), Full (12Mbit/s) and Low (1.5Mbit/s) speed communication and On-
The-Go
eight pipes/endpoints
2368 of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
Flexible Pipe/Endpoint configuration and management with dedicated DMA channels
On-Chip UTMI transceiver including Pull-Ups/Pull-downs
On-Chip OTG pad including VBUS analog comparator
Max. Size
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
512 bytes
64 bytes
describes the hardware configuration of the USB MCU device.
Max. Nb. Banks
1
2
2
2
2
2
2
2
DMA
N
Y
Y
Y
Y
Y
Y
Y
Isochronous/Bulk/Interrupt/Control
Isochronous/Bulk/Interrupt/Control
Isochronous/Bulk/Interrupt/Control
Isochronous/Bulk/Interrupt/Control
Isochronous/Bulk/Interrupt/Control
Isochronous/Bulk/Interrupt/Control
Isochronous/Bulk/Interrupt
AT32UC3A3/A4
Control
Type
630