AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 228

IC MCU 64KB FLASH 144LQFP

AT32UC3A364-ALUT

Manufacturer Part Number
AT32UC3A364-ALUT
Description
IC MCU 64KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A364-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Number Of I /o
110
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
96 KB
Interface Type
IrDA/SCI/SCIF/UDI
Maximum Clock Frequency
66 MHz
Number Of Timers
3
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
110
Ram Memory Size
64KB
Cpu Speed
66MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A364-ALUT
Manufacturer:
Atmel
Quantity:
10 000
Figure 16-9. Low Power Mode Behavior
16.7.6.3
32072C–AVR32–2010/03
SDRAMC_A[12:0]
SDCKE
D[15:0]
(input)
NCS[1]
SDCK
RAS
CAS
Deep power-down mode
This mode is selected by writing the value three to the LPR.LPCB field. When this mode is acti-
vated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
When this mode is enabled, the user must not access to the SDRAM until a new initialization
sequence is done (See
This is described in
Row n
T
RCD
= 3
Col a
Figure 16-10 on page
Section
CAS = 2
Col b
Dna
16.7.1).
Col c
Dnb
Col d
229.
Dnc
Col e
Dnd
Col f
Dne
Dnf
AT32UC3A3/A4
Low Power Mode
228

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