AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 853

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• TRTYP: Transfer Type
• TRDIR: Transfer Direction
• TRCMD: Transfer Command
• MAXLAT: Max Latency for Command to Response
• OPDCMD: Open Drain Command
• SPCMD: Special Command
32072C–AVR32–2010/03
SPCMD
TRCMD
others
TRTYP
others
Writing a zero to this bit will configure the transfer direction as write transfer.
Writing a one to this bit will configure the transfer direction as read transfer.
Writing a zero to this bit will configure a 5-cycle max latency.
Writing a one to this bit will configure a 64-cycle max latency.
Writing a zero to this bit will configure the push-pull command.
Writing a one to this bit will configure the open-drain command.
0
1
2
3
4
5
0
1
2
3
0
1
2
3
4
5
Command
Not a special CMD.
Initialization CMD:
74 clock cycles for initialization sequence.
Synchronized CMD:
Wait for the end of the current data block transfer before sending the pending command.
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the
command line.
Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
Interrupt response:
Corresponds to the Interrupt Mode (CMD40).
Reserved
Transfer Type
No data transfer
Start data transfer
Stop data transfer
Reserved
Transfer Type
MMC/SDCard Single Block
MMC/SDCard Multiple Block
MMC Stream
Reserved
SDIO Byte
SDIO Block
Reserved
AT32UC3A3/A4
853