AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 214

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.7.4
Register Name:
Access Type:
Offset:
Reset Value:
• PS: Page Size
• PMEN: Page Mode Enabled
• TDFMODE: TDF Optimization
• TDFCYCLES: Data Float Time
32072C–AVR32–2010/03
PS
0
1
2
3
31
23
15
–
–
–
7
–
If page mode is enabled, this field indicates the size of the page in bytes.
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
1: TDF optimization is enabled. The number of TDF wait states is optimized using the setup period of the next read/write
access.
0: TDF optimization is disabled.The number of TDF wait states is inserted before the next access begins.
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the
read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDFCYCLES period. The external
bus cannot be used by another chip select during TDFCYCLES plus one cycles. From 0 up to 15 TDFCYCLES can be set.
Mode Register
Page Size
4-byte page
8-byte page
16-byte page
32-byte page
30
22
14
–
–
–
6
–
MODE
Read/Write
0x0C + CS_number*0x10
0x10002103
29
21
13
–
5
EXNWMODE
DBW
PS
TDFMODE
28
20
12
4
27
19
11
–
–
3
–
26
18
10
–
–
2
–
TDFCYCLES
WRITEMODE
AT32UC3A3/A4
25
17
–
9
–
1
READMODE
PMEN
BAT
24
16
8
0
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