AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 219

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.5
16.5.1
Figure 16-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
16.5.2
32072C–AVR32–2010/03
Application Example
Hardware Interface
Software Interface
SDRAMC_A[0-12]
Controller
SDRAM
DQM[0-1]
SDCKE
D0-D31
NCS[1]
SDWE
SDCK
RAS
CAS
BA0
BA1
Table 16-1.
Figure 16-2 on page 219
bus width. It is important to note that this example is given for a direct connection of the devices
to the SDRAMC, without External Bus Interface or I/O Controller multiplexing.
The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows
mapping different memory types according to the values set in the SDRAMC Configuration Reg-
ister (CR).
The SDRAMC’s function is to make the SDRAM device access protocol transparent to the user.
Table 16-2 on page 220
ping seen by the user in correlation with the device structure. Various configurations are
illustrated.
Name
DQM[1:0]
SDRAMC_A[12:0]
D[15:0]
I/O Lines Description
DQM0
D0-D7
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
2Mx8
Description
Data Mask Enable Signals
Address Bus
Data Bus
A0-A9 A11
to
shows an example of SDRAM device connection using a 16-bit data
Table 16-4 on page 220
A10
BA0
BA1
SDRAMC_A10
BA1
BA0
illustrate the SDRAM device memory map-
D8-D15
DQM1
D0-D7
CS
CLK
CKE
RAS
CAS
WE
DQM
SDRAM
2Mx8
Type
Output
Output
Input/Output
A0-A9 A11
AT32UC3A3/A4
BA0
BA1
A10
SDRAMC_A10
BA1
BA0
Active Level
High
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