AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 760

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

27.6.1.6
27.6.2
27.6.2.1
32072C–AVR32–2010/03
Capture Operating Mode
Trigger
Capture registers A and B
A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a fourth external trigger is available to each mode.
The following triggers are common to both modes:
The channel can also be configured to have an external trigger. In Capture mode, the external
trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event
can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external
event can then be programmed to perform a trigger by writing a one to the External Event Trig-
ger Enable bit in CMRn (CMRn.ENETRG).
If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period
in order to be detected.
Regardless of the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value can be read differently from zero just after a
trigger, especially when a low frequency signal is selected as the clock.
This mode is entered by writing a zero to the CMRn.WAVE bit.
Capture mode allows the TC channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are considered as
inputs.
Figure 27-4 on page 762
ture mode.
Registers A and B (RA and RB) are used as capture registers. This means that they can be
loaded with the counter value when a programmable event occurs on the signal TIOA.
The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of
the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA
edge for the loading of the RB register.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in
SRn (SRn.LOVRS). In this case, the old value is overwritten.
• Software Trigger: each channel has a software trigger, available by writing a one to the
• SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the
• Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the
Software Trigger Command bit in CCRn (CCRn.SWTRG).
same effect as a software trigger. The SYNC signals of all channels are asserted
simultaneously by writing a one to the Synchro Command bit in the BCR register
(BCR.SYNC).
counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn
(CMRn.CPCTRG) is written to one.
shows the configuration of the TC channel when programmed in Cap-
AT32UC3A3/A4
760