AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 453

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.9.1
Name:
Access Type:
Offset:
Reset Value:
• TENBIT: Ten Bit Address Match
• ADR: Slave Address
• SOAM: Stretch Clock on Address Match
• CUP: NBYTES Count Up
• ACK: Slave Receiver Data Phase ACK Value
• PECEN: Packet Error Checking Enable
• SMHH: SMBus Host Header
• SMDA: SMBus Default Address
• SMBALERT: SMBus Alert
32072C–AVR32–2010/03
SWRST
31
23
15
7
-
Write this bit to zero to disable Ten Bit Address Match.
Write this bit to one to enable Ten Bit Address Match.
Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise.
Writing this bit to zero will not strech bus clock after address match.
Writing this bit to one will strech bus clock after address match.
Writing this bit to zero causes NBYTES to count down (decrement) per byte transferred.
Writing this bit to one causes NBYTES to count up (increment) per byte transferred.
Writing this bit to zero causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode.
Writing this bit to one causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode.
Writing this bit to zero disables SMBus PEC (CRC) generation and check.
Writing this bit to one enables SMBus PEC (CRC) generation and check.
Writing this bit to zero causes TWIS not to acknowledge the SMBus Host Header.
Writing this bit to one causes TWIS to acknowledge the SMBus Host Header.
Writing this bit to zero causes TWIS not to acknowledge the SMBus Default Address.
Writing this bit to one causes TWIS to acknowledge the SMBus Default Address.
Writing this bit to zero causes TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response
Address (ARA).
Writing this bit to one causes TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address
(ARA).
Control Register
SOAM
30
22
14
6
-
-
CR
Read/Write
0x00
0x00000000
CUP
29
21
13
5
-
-
STREN
ACK
28
20
12
4
-
ADR[7:0]
GCMATCH
PECEN
27
19
11
3
-
SMATCH
TENBIT
SMHH
26
18
10
2
AT32UC3A3/A4
SMEN
SMDA
25
17
9
1
ADR[9:8]
SMBALERT
SEN
24
16
8
0
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