AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 101

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.6.2
Name:
Access Type:
Offset:
Reset Value:
• IRR: Interrupt Request line
32072C–AVR32–2010/03
IRR[32*x+31]
IRR[32*x+23]
IRR[32*x+15]
IRR[32*x+7]
31
23
15
7
This bit is cleared when no interrupt request is pending on this input request line.
This bit is set when an interrupt request is pending on this input request line.
The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, for a total of 2048 possible
input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The
IRRs are sampled continuously, and are read-only.
Interrupt Request Registers
IRR[32*x+30]
IRR[32*x+22]
IRR[32*x+14]
IRR[32*x+6]
30
22
14
IRR0...IRR63
Read-only
0x0FF - 0x1FC
N/A
6
IRR[32*x+29]
IRR[32*x+21]
IRR[32*x+13]
IRR[32*x+5]
29
21
13
5
IRR[32*x+28]
IRR[32*x+20]
IRR[32*x+12]
IRR[32*x+4]
28
20
12
4
IRR[32*x+27]
IRR[32*x+19]
IRR[32*x+11]
IRR[32*x+3]
27
19
11
3
IRR[32*x+26]
IRR[32*x+18]
IRR[32*x+10]
IRR[32*x+2]
26
18
10
2
AT32UC3A3/A4
IRR[32*x+25]
IRR[32*x+17]
IRR[32*x+9]
IRR[32*x+1]
25
17
9
1
IRR[32*x+24]
IRR[32*x+16]
IRR[32*x+8]
IRR[32*x+0]
24
16
8
0
101