AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 509

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.7.1.4
24.7.2
32072C–AVR32–2010/03
Transmitter Operations
Serial clock ratio considerations
Figure 24-7. Receiver Clock Management
The transmitter and the receiver can be programmed to operate with the clock signals provided
on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode
data transfers. In this case, the maximum clock speed allowed on the RX_CLOCK pin is:
In addition, the maximum clock speed allowed on the TX_CLOCK pin is:
A transmitted frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by writing to the TCMR register. See
The frame synchronization is configured by writing to the Transmit Frame Mode Register
(TFMR). See
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the TCMR register. Data is written by the user to the Transmit Holding
Register (THR) then transferred to the shift register according to the data format selected.
When both the THR and the transmit shift registers are empty, the Transmit Empty bit is set in
the Status Register (SR.TXEMPTY). When the THR register is transferred in the transmit shift
register, the Transmit Ready bit is set in the SR register (SR.TXREADY) and additional data can
be loaded in the THR register.
Transmitter
Divider
RX_CLOCK
Clock
Clock
– CLK_SSC divided by two if RX_FRAME_SYNC is input.
– CLK_SSC divided by three if RX_FRAME_SYNC is output.
– CLK_SSC divided by six if TX_FRAME_SYNC is input.
– CLK_SSC divided by two if TX_FRAME_SYNC is output.
Section
24.7.5.
MUX
CKS
CKO
Controller
Tri-state
MUX
INV
CKI
Data Transfer
AT32UC3A3/A4
Section
Controller
Tri-state
CKG
24.7.4.
Receiver
Output
Clock
Clock
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