AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 839

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30.6.4.1
30.6.4.2
30.6.4.3
32072C–AVR32–2010/03
WRITE_SINGLE_BLOCK operation using DMA Controller
READ_SINGLE_BLOCK operation using DMA Controller
WRITE_MULTIPLE_BLOCK
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
6. Write a one to the DMA Transfer done bit in IER register (IER.DMADONE).
7. Issue a WRITE_SINGLE_BLOCK command.
8. Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set.
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
6. Write a one to the IER.DMADONE bit.
7. Issue a READ_SINGLE_BLOCK command.
8. Wait for SR.DMADONE bit is set.
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
5. Program the DMA register with the following fields:
6. Write a one to the IER.DMADONE bit.
7. Issue a WRITE_MULTIPLE_BLOCK command.
8. Wait for DMA chained buffer transfer complete interrupt.
c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set
– Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET).
– Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE).
– Write a one to he DMA.DMAEN bit to enable DMA hardware handshaking in the
d. Check that the SR.XFRDONE bit is set.
– Write zero to the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI.
a. Check that the SR.XFRDONE bit is set.
block of data.
– Write the dma_offset in the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
MCI.
AT32UC3A3/A4
839