AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 873

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

31. Memory Stick Interface (MSI)
31.1
31.2
Figure 31-1. Read packet
32072C–AVR32–2010/03
Features
Overview
SDIO / DATA[3:0]
Rev: 2.1.0.0
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The Memory Stick Interface (MSI) is a host controller that supports Memory Stick Version 1.X
and Memory Stick PRO.
The communication protocol with the Memory Stick is started by write from the CPU to the com-
mand register. When the protocol finishes, the CPU is notified that the protocol has ended by an
interrupt request. When the protocol is started and enters the data transfer state, data is
requested by issuing a DMA transfer request (via DMACA) or an interrupt request to the CPU.
The RDY time out time when the handshake state (BS2 in read protocol, BS3 for write protocol)
is established in communication with the Memory Stick can be designated as the number of
Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has
ended due to a time out error by an interrupt request.
CRC circuit can be set off for test mode purpose. When CRC is off, CRC is not added to the data
transmitted to the Memory Stick.
An interrupt request can also be issued to the CPU when a Memory Stick is inserted or removed.
Memory Stick ver. 1.x & Memory Stick PRO support
Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.)
Data transmit/receive FIFO of 64 bits x 4
16 bits CRC circuit
DMACA transfer support
Card insertion/removal detection
SCLK
BS
Memory Stick
INT
BS0
BS1
Host
TPC
BS2
RDY/BSY
DATA
Memory Stick
BS3
AT32UC3A3/A4
CRC
BS0
INT
873