AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 208

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 15-33. Page Mode Read Protocol (Address MSB and LSB Are Defined in
15.6.9.2
32072C–AVR32–2010/03
A[MSB]
D[15:0]
A[LSB]
CLK_SMC
NRD
NCS
Byte access type in page mode
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
PULSE.NCSRDPULSE field value. The pulse length of subsequent accesses within the page
are defined using the PULSE.NRDPULSE field value.
In page mode, the programming of the read timings is described in
Table 15-7.
The SMC does not check the coherency of timings. It will always apply the NCSRDPULSE tim-
ings as page access timing (t
programmed value for t
The byte access type configuration remains active in page mode. For 16-bit or 32-bit page mode
devices that require byte selection signals, configure the MODE.BAT bit to zero (byte select
access type).
Parameter
READMODE
NCSRDSETUP
NCSRDPULSE
NRDSETUP
NRDPULSE
NRDCYCLE
NCSRDPULSE
Programming of Read Timings in Page Mode
t
pa
Value
‘x’
‘x’
t
‘x’
t
‘x’
pa
sa
pa
is shorter than the programmed value for t
pa
) and the NRDPULSE for accesses to the page (t
Definition
No impact
No impact
Access time of first access to the page
No impact
Access time of subsequent accesses in the page
No impact
NRDPULSE
t
sa
Table 15-6 on page
NRDPULSE
t
sa
AT32UC3A3/A4
Table 15-7 on page
sa
.
207)
sa
), even if the
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