AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 321

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.8.1
19.8.1.1
19.8.1.2
19.8.2
32072C–AVR32–2010/03
Software Handshaking
Hardware Handshaking
Burst Transactions
Single Transactions
Software selects between the hardware or software handshaking interface on a per-channel
basis. Software handshaking is accomplished through memory-mapped registers, while hard-
ware handshaking is accomplished using a dedicated handshaking interface.
When the slave peripheral requires the DMACA to perform a DMA transaction, it communicates
this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMA trans-
action. These software registers are used to implement the software handshaking interface.
The HS_SEL_SRC/HS_SEL_DST bit in the CFGx channel configuration register must be set to
enable software handshaking.
When the peripheral is not the flow controller, then the last transaction registers LstSrcReg and
LstDstReg are not used, and the values in these registers are ignored.
Writing a 1 to the ReqSrcReg[x]/ReqDstReg[x] register is always interpreted as a burst transac-
tion request, where x is the channel number. However, in order for a burst transaction request to
start, software must write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] register.
You can write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x]
registers in any order, but both registers must be asserted in order to initiate a burst transaction.
Upon completion of the burst transaction, the hardware clears the SglReqSrcReg[x]/SglReqD-
stReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers.
Writing a 1 to the SglReqSrcReg/SglReqDstReg initiates a single transaction. Upon completion
of the single transaction, both the SglReqSrcReg/SglReqDstReg and ReqSrcReg/ReqDstReg
bits are cleared by hardware. Therefore, writing a 1 to the ReqSrcReg/ReqDstReg is ignored
while a single transaction has been initiated, and the requested burst transaction is not serviced.
Again, writing a 1 to the ReqSrcReg/ReqDstReg register is always a burst transaction request.
However, in order for a burst transaction request to start, the corresponding channel bit in the
SglReqSrcReg/SglReqDstReg must be asserted. Therefore, to ensure that a burst transaction is
serviced, you must write a 1 to the ReqSrcReg/ReqDstReg before writing a 1 to the SglReqSr-
cReg/SglReqDstReg register.
Software can poll the relevant channel bit in the SglReqSrcReg/ SglReqDstReg and ReqSr-
cReg/ReqDstReg registers. When both are 0, then either the requested burst or single
transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled
and unmasked in order to generate an interrupt when the requested source or destination trans-
action has completed.
Note:
There are 11 hardware handshaking interfaces between the DMACA and peripherals. Refer to
the module configuration chapter for the device-specific mapping of these interfaces.
The transaction-complete interrupts are triggered when both single and burst transactions are
complete. The same transaction-complete interrupt is used for both single and burst transactions.
AT32UC3A3/A4
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