AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 71

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.6.14
Name:
Access Type:
Offset:
Reset Value:
• BOD33: Brown-out 3V3 Reset
• JTAGHARD: JTAG Hard Reset
• OCDRST: OCD Reset
• CPUERR: CPU Error
• JTAG: JTAG reset
• WDT: Watchdog Reset
• EXT: External Reset Pin
• BOD: Brown-out Reset
• POR Power-on Reset
32072C–AVR32–2010/03
CPUERR
31
23
15
7
-
-
-
The CPU was reset due to the supply voltage 3V3 being lower than the brown-out threshold level.
The chip was reset by setting the bit RC_OCD in the JTAG reset register or by using the JTAG HALT instruction.
The CPU was reset because the RES strobe in the OCD Development Control register has been written to one.
The CPU was reset because it had detected an illegal access.
The CPU was reset by setting the bit RC_CPU in the JTAG reset register.
The CPU was reset because of a watchdog timeout.
The CPU was reset due to the RESET pin being asserted.
The CPU was reset due to the supply voltage 1V8 being lower than the brown-out threshold level.
The CPU was reset due to the supply voltage being lower than the power-on threshold level.
Reset Cause Register
30
22
14
RCAUSE
Read-only
0x140
0x00000000
6
-
-
-
-
29
21
13
5
-
-
-
-
JTAG
28
20
12
4
-
-
-
WDT
27
19
11
3
-
-
-
BOD33
EXT
26
18
10
2
-
-
AT32UC3A3/A4
JTAGHARD
BOD
25
17
9
1
-
-
OCDRST
POR
24
16
8
0
-
-
71