AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 283

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.7
18.7.1
Table 18-1.
18.7.2
Table 18-2.
32072C–AVR32–2010/03
0x00C
0x01C
0x02C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x028
(0x000 - 0x03F)+m*0x040
User Interface
Offset
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
Address Range
0x000 - 0x03F
0x040 - 0x07F
Memory Map Overview
Channel Memory Map
0x800-0x830
0x834
PDCA Register Memory Map
PDCA Channel Configuration Registers
...
The channels are mapped as shown in
isters, shown in
Note:
Memory Address Reload Register
Transfer Counter Reload Register
Memory Address Register
Peripheral Select Register
Transfer Counter Register
Interrupt Disable Register
Interrupt Enable Register
Interrupt Status Register
Interrupt Mask Register
1. The reset values are device specific. Please refer to the Module Configuration section at the
Control Register
Status Register
Mode Register
end of this chapter.
Register
Table
18-2, where n is the channel number.
DMA channel m configuration registers
DMA channel 0 configuration registers
DMA channel 1 configuration registers
Performance Monitor registers
Table
Register Name
Version register
MARR
18-1. Each channel has a set of configuration reg-
TCRR
MAR
PSR
TCR
IMR
IER
IDR
ISR
MR
Contents
CR
SR
...
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Access
AT32UC3A3/A4
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
-
(1)
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