AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 244

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3
17.4
17.4.1
17.4.2
17.4.3
17.4.4
32072C–AVR32–2010/03
Block Diagram
Product Dependencies
I/O Lines
Power Management
Clocks
Interrupts
Figure 17-1. ECCHRS Block Diagram
In order to use this module, other parts of the system must be configured correctly, as described
below.
The ECCHRS signals pass through the External Bus Interface module (EBI) where they are
multiplexed.
The programmer must first configure the I/O Controller to assign the EBI pins corresponding to
the Static Memory Controller (SMC)
sponding to
the I/O Controller.
If the CPU enters a sleep mode that disables clocks used by the ECCHRS, the ECCHRS will
stop functioning and resume operation after the system wakes up from sleep mode.
The clock for the ECCHRS bus interface (CLK_ECCHRS) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ECCHRS before disabling the clock, to avoid freezing the ECCHRS in an undefined
state.
The ECCHRS interrupt request line is connected to the interrupt controller. Using the ECCHRS
interrupt requires the interrupt controller to be programmed first.
NAND Flash
SmartMedia
Controller
Memory
Static
Logic
SMC
signals are not used by the application, they can be used for other purposes by
Partial Syndrome
Encoder RS4
Ctrl/ECC 1bit Algorithm
signals to their peripheral function. If I/O lines of the EBI corre-
HECC
Rom 1024x10
Peripheral Bus
Polynomial
GF(2 )
process
ECC Controller
10
AT32UC3A3/A4
User Interface
Error Evaluator
Chien Search
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