AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 215

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• DBW: Data Bus Width
• BAT: Byte Access Type
• EXNWMODE: External WAIT Mode
• WRITEMODE: Write Mode
32072C–AVR32–2010/03
EXNWMODE
DBW
BAT
This field is used only if DBW defines a 16-bit data bus.
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the
read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for
the read and write controlling signal.
1: The write operation is controlled by the NWE signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setup of NCS.
0
1
2
3
0
1
2
3
0
1
External NWAIT Mode
Disabled:
the NWAIT input signal is ignored on the corresponding chip select.
Reserved
Frozen Mode:
if asserted, the NWAIT signal freezes the current read or write cycle. after deassertion, the read or write cycle
is resumed from the point where it was stopped.
Ready Mode:
the NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read
or write signal, to complete the access. If high, the access normally completes. If low, the access is extended
until NWAIT returns high.
Data Bus Width
8-bit bus
16-bit bus
Reserved
Reserved
Byte Access Type
Byte select access type:
Write operation is controlled using NCS, NWE, NBS0, NBS1
Read operation is controlled using NCS, NRD, NBS0, NBS1
Byte write access type:
Write operation is controlled using NCS, NWR0, NWR1
Read operation is controlled using NCS and NRD
AT32UC3A3/A4
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