AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 318

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32072C–AVR32–2010/03
Gather is enabled by writing a ‘1’ to the CTLx.SRC_GATHER_EN bit. The CTLx.SINC field
determines if the address is incremented, decremented or remains fixed when a gather bound-
ary is reached. If the CTLx.SINC field indicates a fixed-address control throughout a DMA
transfer, then the CTLx.SRC_GATHER_EN bit is ignored and the gather feature is automatically
disabled.
Note: For multi-block transfers, the counters that keep track of the number of transfer left to
reach a gather/scatter boundary are re-initialized to the source gather count (SGRx.SGC) and
destination scatter count (DSRx.DSC), respectively, at the start of each block transfer.
Figure 19-4. Destination Scatter Transfer
Scatter Increment
Scatter Increment
A0 + 0x218
A0 + 0x210
A0 + 0x208
A0 + 0x200
A0 + 0x118
A0 + 0x110
A0 + 0x108
A0 + 0x100
A0 + 0x018
A0 + 0x010
A0 + 0x008
A0
System Memory
0 x 080
0 x 080
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
d3
d7
d4
d0
d11
d8
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
CTLx.DST_TR_WIDTH = 3'b011 (64bit/8 = 8 bytes)
DSR.DSI = 16
DSR.DSC = 4
DSR.DSI * 8 = 0x80 (Scatter Increment in bytes)
Scatter Boundary A0 + 0x220
Scatter Boundary A0 + 0x120
Scatter Boundary A0 + 0x020
AT32UC3A3/A4
Data Stream
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