AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 59

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.6.4
Name:
Access Type:
Offset:
Reset Value:
• PLLTEST: PLL Test
• PLLCOUNT: PLL Count
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
• PLLOPT: PLL Option
32072C–AVR32–2010/03
PLLOPT[0]: VCO frequency
0
1
PLLOPT[1]: Output divider
0
1
PLLTEST
31
23
15
7
-
-
-
Reserved for internal use. Always write to 0.
Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
These fields determine the ratio of the PLL output frequency to the source oscillator frequency. Formula is detallied in
the PLL” on page 44
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range
PLLOPT[1]: Enable the extra output divider
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time)
PLL Control Registers
30
22
14
PLL0,1
Read/Write
0x20-0x24
0x00000000
6
-
-
-
-
Description
160MHz<f
80MHz<f
f
f
PLL
PLL
= f
29
21
13
= f
5
-
-
-
vco
vco
vco
/2
vco
<180MHz
<240MHz
28
20
12
4
-
-
PLLOPT
27
19
11
3
PLLCOUNT
26
18
10
2
PLLMUL
PLLDIV
AT32UC3A3/A4
PLLOSC
25
17
9
1
PLLEN
”Enabling
24
16
8
0
59