AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 708

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• SHORTPACKET: Short Packet Interrupt
• STALLEDI: STALLed Interrupt
• CRCERRI: CRC Error Interrupt
• OVERFI: Overflow Interrupt
• NAKINI: NAKed IN Interrupt
• HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt
• NAKOUTI: NAKed OUT Interrupt
• HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt
• UNDERFI: Underflow Interrupt
32072C–AVR32–2010/03
By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence
should be Data0.
For High-bandwidth isochronous endpoint, an EPnINT interrupt is triggered if:
- MDATAE is one and a MData packet has been received (DTSEQ=MData and RXOUTI is one).
- DATAXE is one and a Data0/1/2 packet has been received (DTSEQ=Data0/1/2 and RXOUTI is one)
This bit is set for non-control OUT endpoints, when a short packet has been received.
This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of
isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and
the Automatic Switch (AUTOSW) bit are written to one.
This triggers an EPnINT interrupt if SHORTPACKETE is one.
This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a
one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one.
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the
bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the
packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first
bytes of the packet that fit in.
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT
interrupt if NAKINE is one.
This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the micro-frame, if less than N
transaction has been completed by the USBB without underflow error. This may occur in case of a missing IN token. In this
case, the bank are flushed out to ensure the data synchronization between the host and the device. This triggers an EPnINT
interrupt if HBISOFLUSHE is one.
This bit is cleared when the HBISOFLUSHIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT
interrupt if NAKOUTE is one.
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the microframe, if less than N
bank was written by the cpu within this micro-frame. This triggers an EPnINT interrupt if HBISOINERRE is one.
This bit is cleared when the HBISOINERRIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if
UNDERFE is one.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then
automatically sent by the USBB.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not
fast enough. The packet is lost.
AT32UC3A3/A4
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