AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 931

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

34.3
34.3.1
34.3.2
32072C–AVR32–2010/03
On-Chip Debug (OCD)
Features
Overview
Rev: 1.4.2.1
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Debugging on the AT32UC3A3 is facilitated by a powerful On-Chip Debug (OCD) system. The
user accesses this through an external debug tool which connects to the JTAG port and the Aux-
iliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based
debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:
In addition to the mandatory Nexus debug features, the AT32UC3A3 implements several useful
OCD features, such as:
The OCD features are controlled by OCD registers, which can be accessed by JTAG when the
NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly
using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based
on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical
Reference Manual.
• Basic run-time control
• Program breakpoints
• Data breakpoints
• Program trace
• Ownership trace
• Data trace
• Debug Communication Channel between CPU and JTAG
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support
Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
JTAG access to all on-chip debug functions
Advanced program, data, ownership, and watchpoint trace supported
NanoTrace JTAG-based trace access
Auxiliary port for high-speed trace information
Hardware support for 6 program and 2 data breakpoints
Unlimited number of software breakpoints supported
Automatic CRC check of memory regions
AT32UC3A3/A4
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