AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 45

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.5.5
7.5.5.1
32072C–AVR32–2010/03
PLL0 clock
Osc0 clock
Slow clock
Synchronous Clocks
Selecting PLL or oscillator for the main clock
MCSEL
The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the
common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main
clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from
any tapping of this prescaler, or the undivided main clock, as long as f
nous clock source can be changed on-the fly, responding to varying load in the application. The
clock domains can be shut down in sleep mode, as described in
clocks for each module in the four domains can be individually masked, to avoid power con-
sumption in inactive modules.
Figure 7-4.
The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default,
the main clock will be connected to the slow clock. The user can connect the main clock to Oscil-
lator 0 or PLL0 by writing the MCSEL field in the Main Clock Control Register (MCCTRL). This
must only be done after that unit has been enabled, otherwise a deadlock will occur. Care
should also be taken that the new frequency of the synchronous clocks does not exceed the
maximum frequency for each clock domain.
Prescaler
instruction
Synchronous Clock Generation
Sleep
CPUSEL
CPUDIV
0
1
Controller
Main clock
Sleep
CPUMASK
Mask
Section
AT32UC3A3/A4
CPU
7.5.7. Additionally, the
≥ f
APBB clocks
PBA,B,
APBAclocks
CPU clocks
AHB clocks
. The synchro-
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