AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 660

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.7.3.8
26.7.3.9
26.7.3.10
32072C–AVR32–2010/03
Remote wake-up
Management of control pipes
Management of IN pipes
When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the
following host requests will be performed using the default device address 0.
The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to
zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend
state 3ms later.
The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
When the host controller detects a non-idle state on the USB bus, it set the Host Wake-Up inter-
rupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K
state), the Upstream Resume Received Interrupt (RXRSMI) bit in UHINT is set. The user has to
generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send
USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before
writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no
effect.
A control transaction is composed of three stages:
The user has to change the pipe token according to each stage.
For the control pipe, and only for it, each token is assigned a specific initial data toggle
sequence:
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read which acknowledges or not the bank when it is empty.
The pipe must be configured first.
When the host requires data from the device, the user has to select beforehand the IN request
mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):
The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE)
field in UPCONn is zero).
The Received IN Data Interrupt (RXINI) bit in UPSTAn is set at the same time as the FIFO Con-
trol (FIFOCON) bit in UPCONn when the current bank is full. This triggers a PnINT interrupt if the
Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one.
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
• SETUP: Data0
• IN: Data1
• OUT: Data1
• When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before
• When INMODE is written to one, the USBB will perform IN requests endlessly when the pipe
freezing the pipe.
is not frozen by the user.
AT32UC3A3/A4
660