AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 350

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.12.4
Name:
Access Type:
Offset:
Reset Value:
This register contains fields that control the DMA transfer. The CTLxL register is part of the block descriptor (linked list item)
when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is
enabled.
• LLP_SRC_EN
Block chaining is only enabled on the source side if the LLP_SRC_EN field is high and LLPx.LOC is non-zero.
• LLP_DST_EN
Block chaining is only enabled on the destination side if the LLP_DST_EN field is high and LLPx.LOC is non-zero.
• SMS: Source Master Select
Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from
Table 19-4.
32072C–AVR32–2010/03
SMS
0
1
Other
DINC[0]
DMS[0]
31
23
15
7
SRC_MSIZE[1:0]
Control Register for Channel x Low
Source Master Select
HSB Master
HSB master 1
HSB master 2
Reserved
30
22
14
6
CTLxL
Read/Write
0x018 + [x * 0x58]
0x00304801
SRC_TR_WIDTH
TT_FC
29
21
13
5
DEST_MSIZE
LLP_SRC_E
28
20
12
N
4
LLP_DST_E
27
19
11
N
3
DST_TR_WIDTH
DST_GATHE
R_EN
26
18
10
2
SINC
SMS
SRC_GATHE
AT32UC3A3/A4
R_EN
25
17
9
1
SRC_MSIZE
DINC[1]
INT_EN
DMS[1]
24
16
[2]
8
0
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