AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 446

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.8.2.4
22.8.2.5
22.8.3
32072C–AVR32–2010/03
Slave Transmitter Mode
Clock Stretching
Bus Errors
Any slave or bus master taking part in a transfer may extend the TWCK low period at any time.
TWIS may extend the TWCK low period after each byte transfer if CR.STREN=1 and:
If CR.STREN=0 and:
If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and
TWIS waits for a new START condition.
If TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it will
enter slave transmitter mode and set SR.TRA
After the address phase, the following is done:
• The address in CR.ADR is checked for address match if CR.SMATCH is set.
• The Alert Response Address is checked for address match if CR.SMAL is set.
• The Default Address is checked for address match if CR.SMDA is set.
• The Host Header Address is checked for address match if CR.SMHH is set.
• Module is in slave transmitter mode, data should be transmitted, but THR is empty, or
• Module is in slave receiver mode, a byte has been received and placed into the internal
• Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains
• Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit
• Module is in slave receiver mode, a byte has been received and placed into the internal
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to
2. Byte to transmit depends on I²C/SMBus mode and CR.PEC:
3. Transmit the correct data byte. Set SR.BTF when done.
4. Update NBYTES. If CR.CUP is set, NBYTES is incremented, otherwise NBYTES is
5. After each data byte has been transferred, the master transmits an ACK or NAK bit. If a
6. If STOP is received, SR.TCOMP and SR.STO will be set.
7. If REPEATED START is received, SR.REP will be set.
shifter, but RHR is full, or
stretched until all address match bits in SR have been cleared.
the value present in THR (the last transmitted byte or reset value), and set SR.URUN.
shifter, but RHR is full: Discard the received byte and set SR.ORUN.
transmit. This is necessary in order to know when to transmit PEC byte. NBYTES can
also be used to count the number of bytes received if using DMA.
– If in I²C mode or CR.PEC=0 or NBYTES!=0: TWIS waits until THR contains a valid
– SMBus mode and CR.PEC=1: If NBYTES=0, the generated PEC byte is
decremented.
NAK bit is received, transfer is finished, and TWIS will wait for a STOP or REPEATED
START. If an ACK bit is received, more data should be transmitted, jump to step 2.
data byte, possibly stretching low period of TWCK. SR.TXRDY indicates the state of
THR.
automatically transmitted instead of a data byte from THR. TWCK will not be
stretched by TWIS.
AT32UC3A3/A4
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