AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 654

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.7.2.14
26.7.2.15
26.7.2.16
32072C–AVR32–2010/03
Underflow
Overflow
HB IsoIn error
If the endpoint uses several banks, the current one can be read while the following one is being
written by the host. Then, when the user clears FIFOCON, the following bank may already be
ready and RXOUTI is set immediately.
In Hi-Speed mode, the PING and NYET protocol is handled by the USBB. For single bank, a
NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the current
packet is acknowledged but there is no room for the next one. For double bank, the USBB
responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted
the data successfully and has room for another data payload (the second bank is free).
This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt
(UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable
(UNDERFE) bit is one.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-
length packet is then automatically sent by the USBB.
An underflow can not occur during OUT stage on a CPU action, since the user may read only if
the bank is not empty (RXOUTI is one or RWALL is one).
An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.
An underflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).
This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn,
what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one.
An overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
An overflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).
This error exists only for high-bandwidth isochronous IN endpoints.
At the end of the micro-frame, if at least one packet has been sent to the host, if less banks than
expected has been validated (by clearing the FIFOCON) for this micro-frame, it set the
HBISOINERRORI bit in UESTAn, what triggers an EPnINT interrupt if the High Bandwidth Iso-
chronous IN Error Interrupt Enable (HBISOINERRORE) bit is one.
For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint
(NBTRANS field in UECFGn is three (three transactions per micro-frame), only two banks are
• The user can read the byte count of the current bank from BYCT to know how many bytes to
• The user reads the data from the current bank by using the USBFIFOnDATA register, until all
• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.
read, rather than polling RWALL.
the expected data frame is read or the bank is empty (in which case RWALL is cleared and
BYCT reaches zero).
AT32UC3A3/A4
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