AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 448

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 22-10. Slave Receiver with Multiple Data Bytes
22.8.5
32072C–AVR32–2010/03
TCOMP
RXR DY
TWD
Using the Peripheral DMA Controller
S
DADR
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the
slave to pull it down in order to generate the acknowledge. The master polls the data line during
this clock pulse.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 22-9. Slave Receiver with One Data Byte
The use of the Peripheral DMA Controller significantly reduces the CPU load. The programmer
can set up ring buffers for the DMA controller, containing data to transmit or free buffer space to
place received data. By initializing NBYTES to 0 before a transfer, and setting CR.CUP,
3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise
4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordi-
5. If STOP is received, SR.TCOMP will be set.
6. If REPEATED START is received, SR.REP will be set.
R
NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is
used.
nary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC
is enabled and the last byte received was a PEC byte (indicated by NBYTES=0), TWIS
will automatically return an ACK if the PEC value was correct, otherwise a NAK will be
returned.
A
DATA n
TCOMP
RXR DY
TWD
A
S
Read RHR
DATA n
DATA (n+1)
DADR
A
DATA (n+1)
Read RHR
R
DAT A (n+m)-1
A
DATA
DAT A (n+m)-1
A
Read RHR
DATA (n+m)
AT32UC3A3/A4
Read RHR
N
P
N
DATA (n+m)
Read RHR
P
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