AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 225

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 16-6. Read Burst with Boundary Row Access
16.7.5
32072C–AVR32–2010/03
SDRAMC_A[12:0]
D[15:0]
NCS[1]
SDWE
SDCK
RAS
CAS
SDRAM Controller Refresh Cycles
Col a
Row n
Col b
Dna
An auto refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto refresh automatically.
The SDRAMC generates these auto refresh commands periodically. An internal timer is loaded
with the value in the Refresh Timer Register (TR) that indicates the number of clock cycles
between successive refresh cycles.
A refresh error interrupt is generated when the previous auto refresh command did not perform.
In this case a Refresh Error Status bit is set in the Interrupt Status Register (ISR.RES). It is
cleared by reading the ISR register.
When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not
delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is
busy and the master is held by a wait signal. See
Col c
Dnb
Col d
Dnc
Dnd
T
RP
= 3
Row m
T
RCD
= 3
Figure 16-7 on page
Col a
CAS = 2
Col b
Dma
AT32UC3A3/A4
Col c
226.
Dmb
Col d
Dmc
Col e
Dmd
Dme
225