AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 723

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.8.3
26.8.3.1
Register Name:
Access Type:
Offset:
Reset Value:
• SPDCONF: Speed Configuration
• RESUME: Send USB Resume
• RESET: Send USB Reset
• SOFE: Start of Frame Generation Enable
32072C–AVR32–2010/03
31
23
15
7
-
-
-
-
This field contains the host speed capability.
Writing a one to this bit will generate a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit has no effect.
This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset
is being sent.
Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.TXRSMI).
0
0
1
1
USB Host Registers
Host General Control Register
SPDCONF
30
22
14
6
-
-
-
-
UHCON
Read/Write
0x0400
0x00000000
0
1
0
1
29
21
13
5
-
-
-
Speed
Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to
the high-speed mode if the downstream peripheral is high-speed capable.
reserved, do not use this configuration
reserved, do not use this configuration
Full-speed: the host remains to full-speed mode whatever is the peripheral speed capability.
SPDCONF
28
20
12
4
-
-
-
27
19
11
3
-
-
-
-
RESUME
26
18
10
2
-
-
-
AT32UC3A3/A4
RESET
25
17
9
1
-
-
-
SOFE
24
16
8
0
-
-
-
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