AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 739

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• NBUSYBK: Number of Busy Banks
• DTSEQ: Data Toggle Sequence
• SHORTPACKETI: Short Packet Interrupt
• RXSTALLDI: Received STALLed Interrupt
• CRCERRI: CRC Error Interrupt
• OVERFI: Overflow Interrupt
• NAKEDI: NAKed Interrupt
32072C–AVR32–2010/03
This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit.
This field indicates the number of busy bank.
For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are
busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this
triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
This field indicates the data PID of the current bank.
For OUT pipe, this field indicates the data toggle of the next packet that will be sent.
For IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
This bit is cleared when the SHORTPACKETIC bit is written to one.
This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.
This bit is cleared when the RXSTALLDIC bit is written to one.
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if
the TXSTPE bit is one.
This bit is cleared when the CRCERRIC bit is written to one.
This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is
triggered if the OVERFIE bit is one.
This bit is cleared when the OVERFIC bit is written to one.
This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.
0
1
1
0
0
1
1
0
0
1
1
NBUSYBK
CURRBK
DTSEQ
1
0
1
0
1
0
1
0
1
0
1
Current Bank
Bank1
Bank2
Reserved
Number of busy bank
All banks are free.
1 busy bank
2 busy banks
reserved
Data toggle sequence
Data0
Data1
reserved
reserved
AT32UC3A3/A4
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