AT32UC3A364-ALUT Atmel, AT32UC3A364-ALUT Datasheet - Page 885

• Manufacturer Part Number: AT32UC3A364-ALUT
• Description: IC MCU 64KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A364-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, WDT
• Number Of I /o: 110
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 96 KB
• Interface Type: IrDA/SCI/SCIF/UDI
• Maximum Clock Frequency: 66 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 110
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATEVK1104 - KIT DEV/EVAL FOR AVR32 AT32UC3AATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

31.7.4
Name :
Access Type :
Offset :
Reset Value :
•
•
•
•
•
•
•
CLKDIV : Clock Division.
RST : Reset. When RST is written, internal synchronous reset is performed.
SRAC : Serial Access Mode. The SRAC cannot be changed during protocol execution.
NOCRC : No CRC computation.
FCLR : FIFO clear.
FDIR : FIFO direction.
REI : Rising Edge Input. When setting parallel mode, set REI=0. This setting cannot be changed during protocol execution.
RST
Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)).
0 : This bit is cleared to 0 after the internal reset is completed.
1 : Writing a 1 starts reset operation.
0 : Write this bit to 0 to set parallel mode.
1 : Write this bit to 1 to set serial mode.
0 : Write 0 to enable CRC output. During read protocol, the CRC check is performed as usual regardless of NOCRC.
1 : Write 1 to disable CRC output. When NOCRC=1, the write protocol is executed without adding the CRC data.
Write 1 to initialize FIFO data. This bit is cleared after the FIFO is initialized.
0 : Write 0 to set the FIFO direction to transmit.
1 : Write 1 to set the FIFO direction to receive.
0 : Write 0 to sample data at the falling edge of SCLK.
1 : Write 1 to sample data at the rising edge of SCLK.
31
23
15
7
-
-
System register
SRAC
30
22
14
SYS
Read/Write
0x0C
0x00004015
6
-
-
29
21
13
5
-
-
-
NOCRC
REI
28
20
12
4
-
CLKDIV
REO
27
19
11
3
-
-
26
18
10
2
-
-
FCLR
BSY
25
17
9
1
-
FDIR
24
16
8
0
-